`timescale 1ns / 1ps

`include "data_width.vh"

// 将以 32 为单位重排后的 64 个数据进行整合，从 2 个 32 分区中选择出有效的数据
module rd_src_p_reorder_block_2 #(parameter
    VERTEX_BRAM_NUM     = `VERTEX_BRAM_NUM,
    VERTEX_BRAM_DWIDTH  = `VERTEX_BRAM_DWIDTH,
    VERTEX_PIPE_NUM     = `VERTEX_PIPE_NUM,
    EDGE_PIPE_NUM       = `EDGE_PIPE_NUM,
    TOT_EDGE_MASK_WIDTH = `TOT_EDGE_MASK_WIDTH,
    TOT_ACC_ID_WIDTH    = `TOT_ACC_ID_WIDTH,
    DST_ID_DWIDTH       = `DST_ID_DWIDTH,
    VERTEX_MASK_WIDTH   = `VERTEX_MASK_WIDTH
    ) (
        input                                                   clk,
        input                                                   front_rst,
        input [VERTEX_BRAM_DWIDTH * VERTEX_BRAM_NUM - 1 : 0]    front_src_p,
        input [VERTEX_BRAM_NUM - 1 : 0]                         front_src_p_valid,
        input                                                   front_rd_src_p_addr_finish,
        input [TOT_EDGE_MASK_WIDTH - 1 : 0]                     front_tot_src_p_mask,
        input [TOT_ACC_ID_WIDTH - 1 : 0]                        front_tot_acc_id,
        input                                                   front_any_dst_data_valid,
        input [DST_ID_DWIDTH * VERTEX_PIPE_NUM - 1 : 0]         front_dst_id,
        input [VERTEX_MASK_WIDTH * VERTEX_PIPE_NUM - 1 : 0]     front_src_p_mask_r,
        input [VERTEX_PIPE_NUM - 1 : 0]                         front_dst_data_valid,
        input                                                   back_stage_edge_full,
        input                                                   back_stage_vertex_full,

        output                                                  rst,
        output                                                  buffer_full_vertex,
        output [VERTEX_BRAM_DWIDTH * EDGE_PIPE_NUM - 1 : 0]     src_p,
        output                                                  src_p_valid,
        output [TOT_EDGE_MASK_WIDTH - 1 : 0]                    tot_src_p_mask,
        output [TOT_ACC_ID_WIDTH - 1 : 0]                       tot_acc_id,
        output                                                  any_dst_data_valid,
        output [DST_ID_DWIDTH * VERTEX_PIPE_NUM - 1 : 0]        dst_id,
        output [VERTEX_MASK_WIDTH * VERTEX_PIPE_NUM - 1 : 0]    src_p_mask_r,
        output [VERTEX_PIPE_NUM - 1 : 0]                        dst_data_valid);
    
    wire                            mask_buffer_empty, mask_buffer_full;
    wire [VERTEX_PIPE_NUM - 1 : 0]  dst_buffer_empty, dst_buffer_full;
    wire [VERTEX_PIPE_NUM - 1 : 0]  data_valid;

    assign buffer_full_vertex = dst_buffer_full[0];
    assign any_dst_data_valid = data_valid[0];

    rd_src_p_reorder_block_2_para_trans P (
        .clk(clk), .front_rst(front_rst),

        .rst(rst));

    rd_src_p_reorder_block_2_edge E1 (
        .clk(clk), .rst(front_rst),
        .front_src_p(front_src_p), .front_src_p_valid(front_src_p_valid),
        .front_rd_src_p_addr_finish(front_rd_src_p_addr_finish),
        .back_stage_edge_full(back_stage_edge_full),

        .src_p(src_p), .src_p_valid(src_p_valid));

    rd_src_p_reorder_block_2_mask M1 (
        .clk(clk), .rst(front_rst),
        .front_tot_src_p_mask(front_tot_src_p_mask), .front_tot_acc_id(front_tot_acc_id),
        .front_any_dst_data_valid(front_any_dst_data_valid), .back_stage_vertex_full(back_stage_vertex_full),

        .buffer_empty(mask_buffer_empty), .buffer_full(mask_buffer_full),
        .tot_src_p_mask(tot_src_p_mask), .tot_acc_id(tot_acc_id));

    generate
        genvar i;
        for (i = 0; i < VERTEX_PIPE_NUM; i = i + 1) begin : M11_2_BLOCK_1
            rd_src_p_reorder_block_2_vertex_single V (
                .clk                        (clk),
                .rst                        (front_rst),
                .front_dst_id               (front_dst_id[(i + 1) * DST_ID_DWIDTH - 1 : i * DST_ID_DWIDTH]),
                .front_src_p_mask_r         (front_src_p_mask_r[(i + 1) * VERTEX_MASK_WIDTH - 1 : i * VERTEX_MASK_WIDTH]),
                .front_dst_data_valid       (front_dst_data_valid[i]),
                .front_any_dst_data_valid   (front_any_dst_data_valid),
                .back_stage_vertex_full     (back_stage_vertex_full),

                .buffer_empty               (dst_buffer_empty[i]),
                .buffer_full                (dst_buffer_full[i]),
                .data_valid                 (data_valid[i]),
                .dst_id                     (dst_id[(i + 1) * DST_ID_DWIDTH - 1 : i * DST_ID_DWIDTH]),
                .src_p_mask_r               (src_p_mask_r[(i + 1) * VERTEX_MASK_WIDTH - 1 : i * VERTEX_MASK_WIDTH]),
                .dst_data_valid             (dst_data_valid[i]));
        end
    endgenerate

endmodule

module rd_src_p_reorder_block_2_para_trans (
    input       clk,
    input       front_rst,

    output reg  rst);
    
    always @ (posedge clk) begin
        rst <= front_rst;
    end

endmodule

module rd_src_p_reorder_block_2_edge #(parameter
    REORDER_LOC_Y_WIDTH = `REORDER_LOC_Y_WIDTH,
    EDGE_PIPE_NUM = `EDGE_PIPE_NUM,
    VERTEX_BRAM_NUM = `VERTEX_BRAM_NUM, VERTEX_BRAM_DWIDTH = `VERTEX_BRAM_DWIDTH
    ) (
        input                                                   clk,
        input                                                   rst,
        input [VERTEX_BRAM_DWIDTH * VERTEX_BRAM_NUM - 1 : 0]    front_src_p,
        input [VERTEX_BRAM_NUM - 1 : 0]                         front_src_p_valid,
        input                                                   front_rd_src_p_addr_finish,
        input back_stage_edge_full,

        output reg [VERTEX_BRAM_DWIDTH * EDGE_PIPE_NUM - 1 : 0] src_p,
        output reg                                              src_p_valid);

    reg [VERTEX_BRAM_DWIDTH * EDGE_PIPE_NUM - 1 : 0] src_buffer;
    reg now_rd_src_p_addr_finish;

    // output
    always @ (posedge clk) begin
        if (rst) begin
            src_p       <= 0;
            src_p_valid <= 1'b0;
        end
        else begin
            if (now_rd_src_p_addr_finish && !back_stage_edge_full) begin
                src_p       <= src_buffer;
                src_p_valid <= 1'b1;
            end
            else begin
                src_p       <= 0;
                src_p_valid <= 1'b0;
            end
        end
    end

    generate
        genvar i;
        // input
        for (i = 0; i < EDGE_PIPE_NUM; i = i + 1) begin: M11_2_BLOCK_2
            always @ (posedge clk) begin
                if (rst) begin
                    src_buffer[(i + 1) * VERTEX_BRAM_DWIDTH - 1 : i * VERTEX_BRAM_DWIDTH] <= 0;
                end
                else begin
                    casex ({front_src_p_valid[i], front_src_p_valid[i + 32]})
                        2'b1x: begin
                            src_buffer[(i + 1) * VERTEX_BRAM_DWIDTH - 1 : i * VERTEX_BRAM_DWIDTH] <= front_src_p[(i + 1) * VERTEX_BRAM_DWIDTH - 1 : i * VERTEX_BRAM_DWIDTH];
                        end
                        2'b01: begin
                            src_buffer[(i + 1) * VERTEX_BRAM_DWIDTH - 1 : i * VERTEX_BRAM_DWIDTH] <= front_src_p[(i + 32 + 1) * VERTEX_BRAM_DWIDTH - 1 : (i + 32) * VERTEX_BRAM_DWIDTH];
                        end
                    endcase
                end
            end
        end
    endgenerate

    // buffer finish
    always @ (posedge clk) begin
        if (rst) begin
            now_rd_src_p_addr_finish <= 1'b0;
        end
        else begin
            now_rd_src_p_addr_finish <= front_rd_src_p_addr_finish;
        end
    end
endmodule

module rd_src_p_reorder_block_2_mask #(parameter
    TOT_EDGE_MASK_WIDTH = `TOT_EDGE_MASK_WIDTH, TOT_ACC_ID_WIDTH = `TOT_ACC_ID_WIDTH
    ) (
        input                                   clk,
        input                                   rst,
        input [TOT_EDGE_MASK_WIDTH - 1 : 0]     front_tot_src_p_mask,
        input [TOT_ACC_ID_WIDTH - 1 : 0]        front_tot_acc_id,
        input                                   front_any_dst_data_valid,
        input                                   back_stage_vertex_full,

        output                                  buffer_empty,
        output                                  buffer_full,
        output [TOT_EDGE_MASK_WIDTH - 1 : 0]    tot_src_p_mask,
        output [TOT_ACC_ID_WIDTH - 1 : 0]       tot_acc_id);

    tot_edge_mask_fifo TEM1 (
        .clk(clk), .srst(rst),
        .din(front_tot_src_p_mask), .wr_en(front_any_dst_data_valid), .rd_en(!back_stage_vertex_full),

        .dout(tot_src_p_mask), .empty(buffer_empty), .prog_full(buffer_full));

    tot_acc_id_fifo TAI1 (
        .clk(clk), .srst(rst),
        .din(front_tot_acc_id), .wr_en(front_any_dst_data_valid), .rd_en(!back_stage_vertex_full),

        .dout(tot_acc_id));

endmodule

module rd_src_p_reorder_block_2_vertex_single #(parameter
    DST_ID_DWIDTH = `DST_ID_DWIDTH, VERTEX_MASK_WIDTH = `VERTEX_MASK_WIDTH
    ) (
        input                               clk,
        input                               rst,
        input [DST_ID_DWIDTH - 1 : 0]       front_dst_id,
        input [VERTEX_MASK_WIDTH - 1 : 0]   front_src_p_mask_r,
        input                               front_dst_data_valid,
        input                               front_any_dst_data_valid,
        input                               back_stage_vertex_full,

        output                              buffer_empty,
        output                              buffer_full,
        output                              data_valid,
        output [DST_ID_DWIDTH - 1 : 0]      dst_id,
        output [VERTEX_MASK_WIDTH - 1 : 0]  src_p_mask_r,
        output                              dst_data_valid);

    dst_id_fifo DI1 (
        .clk(clk), .srst(rst),
        .din(front_dst_id), .wr_en(front_any_dst_data_valid), .rd_en(!back_stage_vertex_full),

        .dout(dst_id), .empty(buffer_empty), .prog_full(buffer_full));

    vertex_mask_fifo VM1 (
        .clk(clk), .srst(rst),
        .din(front_src_p_mask_r), .wr_en(front_any_dst_data_valid), .rd_en(!back_stage_vertex_full),
        
        .dout(src_p_mask_r));

    valid_fifo DDV1 (
        .clk(clk), .srst(rst),
        .din(front_dst_data_valid), .wr_en(front_any_dst_data_valid), .rd_en(!back_stage_vertex_full),
        
        .dout(dst_data_valid), .valid(data_valid));

endmodule